1. Field of the Invention
The present invention relates to EEPROM memories (electrically erasable and programmable memories) and to an improvement in the breakdown threshold of transistors in the presence of a high programming or erase voltage.
2. Description of the Related Art
FIG. 1A is the wiring diagram of a classic EEPROM memory cell 10. The memory cell comprises a floating-gate transistor FGT and a selection transistor ST. The transistor ST comprises a gate G, a drain D (drain terminal) and a source S (source terminal). The transistor FGT also comprises a control gate CG, a drain D and a source S, and also comprises a floating gate FG. The source S of the selection transistor ST is connected to the drain D of the transistor FGT.
FIG. 1B is a cross-section of an example of an embodiment of the memory cell 10 according to the double polysilicon layer technique, and FIG. 1C shows the memory cell seen from above. Three n+ doped regions 3, 4, 5 are formed in a p-type substrate 1. The region 3 forms the source region of the transistor FGT, the region 4 forms the drain region of the transistor FGT and the source region of the transistor ST, and the region 5 forms the drain region of the transistor ST. The floating gate FG of the transistor FGT is formed by a polysilicon pad POLY1A. The gate G of the transistor ST is formed by the intersection of a line of polysilicon POLY1B with the doped regions 4, 5, the line POLY1B forming a word line WL linking the gates of various other selection transistors (not represented). Similarly, the control gate CG of the transistor FGT is formed by the intersection of a line of polysilicon POLY2 with the doped regions 3, 4, the line POLY2 forming a control gate line CGL linking the control gates of various other transistors FGT (not represented). These various polysilicon parts are insulated from the substrate and insulated from one another by a dielectric 2, generally silicon dioxide. Finally, a source contact SC formed above the region 3 links the source of the transistor FGT to a source line SL (not represented). A drain contact DC formed above the region 5 links the drain of the transistor ST to a bit line BL (not represented).
A datum is saved or erased in the memory cell 10 by injecting electric charges into the floating gate FG of the transistor FGT or by extracting electric charges from the floating gate FG. The injection or extraction of charges changes the threshold voltage of the transistor FGT that is then detected by a sense amplifier, the function of which is to transform the “threshold voltage” information into a binary datum, for example equal to 1 when the threshold voltage is negative and equal to 0 when the threshold voltage is positive.
The two processes of injecting and extracting electric charges are performed by tunnel effect (Fowler-Nordheim effect). For this purpose, the floating gate FG has a region that extends above the drain region 4 and in which the separating layer of dielectric 2 is made thinner to form a tunnel window TW. To program the memory cell (injection of charges), a high programming voltage is applied to the drain region of the transistor FGT, via the transistor ST, while the control gate CG is taken to a zero or negative potential. To erase the memory cell, a high erase voltage is applied to the control gate CG while the source region 3 is taken to a zero or negative potential.
The performances of an EEPROM memory are directly linked to the time of injecting or extracting electric charges into floating gates of the memory cells. An efficient memory must have a programming or erasing time as short as possible. This time depends on three parameters that are involved in the transfer of charges by tunnel effect:
1) the thickness of the dielectric forming the tunnel window TW,
2) the value of the high programming or erase voltage,
3) the floating gate coupling factor, i.e., the ratio between, firstly, the capacitive coupling between the floating gate and the control gate and, secondly, the capacitive coupling between the floating gate, the drain, the source, and the substrate.
The thickness of the tunnel dielectric cannot be reduced below a certain threshold, above which the memory cells would have losses of electric charges (“retention loss”) eventually causing a corruption of data (an EEPROM memory being supposed to keep the data saved for several years). It follows that the two main parameters on which the performances of an EEPROM memory rely are the coupling factor and the value of the high programming or erase voltage.
The greater the coupling factor, the faster the programming or erasing process for a determined programming or erase voltage. However, the coupling factor tends to decrease when the size of the memory cells decreases (transistor FGT and ST gate width to length W/L ratio). As the size of transistors is constantly decreasing with the improvement of microelectronic techniques, the paradoxical result is that the new generation memories, having smaller memory cells, need higher programming and erase voltages than the previous generation memories. Thus, the coupling factor represents a major obstacle to the decrease in the size of EEPROM memories without increasing the programming or erasing time.
After all is said and done, the obvious solution to preserve the programming and erasing time of an EEPROM memory the size of the transistors of which must be reduced, is to increase the value of the high programming or erase voltage. However, another technological constraint is also faced, in that MOS transistors have a breakdown threshold which determines the maximum value of the erase or programming voltage that can be applied to interconnected memory cells.
In FIG. 1B, the reference Di designates a breakdown region of a selection transistor ST. This region is a PN substrate-drain junction (and more particularly channel-drain) forming a reverse-biased diode. When the drain region receives a programming voltage while the substrate 1 is linked to the ground (which, in principle, is always the case), the diode Di reaches its breakdown point (threshold voltage of the reverse-biased diode) in the vicinity of a value that is in the order of 12V in the EEPROM memories marketed by the applicant. Thus, the programming voltage cannot be taken above this value.
For a better understanding of the impact of the breakdown phenomenon on the programming and erasing process, FIG. 3 represents an EEPROM memory of the word-erasable type, having memory cells being programmed. It can be seen that the selection transistors ST of vertically aligned memory cells have their respective drains connected to common bit lines BL. For example, selection transistors ST(i,7,k) and ST(i−2,7,k) are connected to a same bit line BL(7,k). Thus, when a high programming voltage Vpp1 is applied to the bit line BL(7,k) to program for example the memory cell comprising the selection transistor ST(i,7,k), this transistor receives a high value gate voltage Vp1 to let the high voltage Vpp1 through while all the other selection transistors connected to this bit line, particularly the transistor ST(i−2,7,k), receive a zero gate voltage and are in the off state. These transistors not involved in the programming process have a lower breakdown threshold than that of the transistor ST(i,7,k) and thus limit the maximum voltage Vpp1 that can be applied to the bit line.
As another example, FIG. 4 represents an EEPROM memory identical to the one in FIG. 3 but having memory cells being erased. The memory comprises control gate transistors, for example transistors CGT(i−2,k) and CGT(i,k), the drains of which are connected to a common control gate line, for example a line CGL(k). When a high erase voltage Vpp1 is applied to the control gate line CGL(k) to erase for example memory cells linked to the transistor CGT(i,k), this transistor receives a high value gate voltage Vp1 to let the high voltage through while all the other transistors linked to this control gate line, particularly the transistor CGT(i−2,k), receive a zero gate voltage and are in the off state. These transistors that are not involved in the erasing process have a breakdown threshold lower than that of the transistor CGT(i,k) and thus limit the maximum voltage Vpp1 that can be applied to the control gate line.